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? vitesse semiconductor corporation page 1 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse features functional description the vs8004 and vs8005 are data conversion devices capable of serial data rates up to 2.5 gb/s, transform- ing 4-bit wide parallel data to serial data and serial data to 4-bit wide parallel data. the vs8004/vs8005 are fabricated in gallium arsenide using the vitesse h-gaas e/d mesfet process which achiev es high speed and lo w power dissipation. these products are packaged in a ceramic 28-pin leaded chip carrier. vs8004 the vs8004 is a high speed 4 bit parallel to serial data con v erter suitable for digital v oice or data communi- cations applications. all inputs and outputs can be used dif ferentially or single-ended. the parallel inputs [d(0:3), nd(0:3)] accept data at rates up to 625 mb/s. the dif ferential serial data output (sd ata, nsdata) presents the data sequentially from the parallel data inputs at rates up to 2.5 gb/s, synchronous with the dif fer- ential high speed clock input (clk, nclk). an internal timing generator recei v es the high speed clock input and di vides it by four to create a dif ferential clock output (clk4, nclk4). this clock signal is pro vided so that incoming parallel signals can be synchronized to arri v e at the input data re gisters simultaneously . an internal bias network is provided at all inputs to simplify capacitive coupling. vs8005 the vs8005 is a high speed 4-bit serial to parallel data con v erter suitable for digital v oice or data commu- nications applications. all inputs and outputs can be used dif ferentially or single-ended. the differential serial data inputs (sdata, nsdat a) accept data at rates up to 2.5 gb/s, synchronous with the dif ferential high speed clock input (clk, nclk). the parallel outputs [d(0:3), nd(0:3)] present the data sequentially at rates up to 625 mb/s. an internal timing generator receiv es the high speed clock input and di vides it by four to create a dif- ferential clock output (clk4, nclk4) which is synchronous with the parallel data outputs. a control input (skip, nskip) is provided to allow realignment of the output parallel word boundaries. skip signal the skip signal is pro vided to allo w realignment of the output parallel 4-bit w ord boundaries. within the current clk4, the rising edge of a skip causes an internal circuit in the vs8005 to hold the current 4-bit w ord output and drop the fth output bit. the sixth output bit will become the msb of the ne xt 4-bit word output; and ? differential or single-ended inputs and outputs ? low power dissipation: 1.5 w (typ. per chip) ? standard ecl power supply: vee = -5.2 v ? av ailable in commercial (0 to +70 c) or indus- trial (-40 to +85 c) temperature ranges ? proven e/d mode gaas technology ? 28-pin leaded ceramic chip carrier ? serial data rates up to 2.5 gb/s ? parallel data rates up to 625 mb/s ? ecl 100k compatible parallel data i/os ? divide-by-4 clock for synchronization of parallel data to interfacing chips ? skip input on demux for realignment of output word boundaries
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 2 ? vitesse semiconductor corporation g52012-0 rev. 2.0 the f alling edge of skip mak es the ne xt three parallel output w ords inv alid (which is equal to three clk4 or twelve clk). after that the outputs will be valid and will have the msb of the output realigned by one bit. f or example, the user nds that the w ord boundary of the output is of f by tw o bits, then he needs to perform tw o skips. he needs to issue one skip , wait for three clk4 c ycles until the output is v alid, then issue another skip, w ait for another three clk4 c ycles. then the outputs will ha v e the bit positions in the right place as dem- onstrated in the following: misaligned by 2 bits: misaligned by 1 bit: realignment done. applications c d g h k l o p s t c d c d h i l m p q t a d e e f i j m n q r a b e f e f j k n o r s b c f g invalid skip 1/2 byte word output d e h i l m p q t a d e d e i j m n q r a b e f f g j k n o r s b c f g f g k l o p s t c d g h invalid skip 1/2 byte word output ?high speed instrumentation and test equipment ?fiber-optic communication ?local area networks ?serialization of computer backplanes ?computer to computer interfaces ?serial control buses for aerospace environments
? vitesse semiconductor corporation page 3 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse figure 1: vs8004 block diagram figure 2: vs8005 block diagram v cc = v v ee = -5.2v 0.26v timing circuit 4:1 mux d nd d1 nd1 d2 nd2 d3 nd3 clk nclk sdata nsdata clk4 nclk4 sdata nsdata clk nclk skip nskip v cc = v timing circuit 1:2 demux 2:4 demux v ee = -5.2v 0.26v d nd d1 nd1 d2 nd2 d3 nd3 clk4 nclk4
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 4 ? vitesse semiconductor corporation g52012-0 rev. 2.0 vs8004 ac characteristics (over recommended operating conditions) figure 3: vs8004 waveforms parameter description min typ max units t clk high speed clock period 400 - - ps t su d( ? :3), nd( ? :3), set-up time with respect to clk4, nclk4 900 - - ps t h d( ? :3), nd( ? :3), hold time with respect to clk4, nclk4 -300 - - ps t tlh (hs), t thl (hs) sdata, nsdata transition time (lo to hi, hi to lo) while driving 50 w to -2.0v - 150 - ps jitter(rms) clk, nclk to sdata, nsdata (max-min), (hi to lo), same part, same pin at constant conditions - <50 - ps t tlh ,t thl ecl output transition time (lo to hi, hi to lo) while driving 50 w (clk4, nclk4, d(0:3), nd(0:3)) to -2.0v - 500 - ps valid data d2 d3 d1 d t clk t su t h t tlh , t thl t tlh , t thl (hs) (hs) d(:3), nd(:3) clk , nclk sdata, nsdata clk4 , nclk4 (1) (1) (1) negative edge is active edge
? vitesse semiconductor corporation page 5 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse vs8005 ac characteristics (over recommended operating conditions) figure 4: vs8005 waveforms parameter description min typ max units t clk high speed clock period (clk, nclk) 400 - - ps t cad clk4, nclk4 to d( 0 :3), nd( 0 :3) - 400 - ps t pwh skip, nskip pulse with (high) 2 - - ns t pwl skip, nskip pulse with (low) 2 - - ns t tlh ,t thl ecl output transition time (low to high & high to lo w) for d(0:3), nd(0:3) and clk4, nclk4 (dri ving 50 w ) - 500 - ps phase margin sdata, nsdata phase timing margin with respect to clk, nclk input: 135 _ - degrees tlh, thl t t t c4d t pwh valid data clk t t pwl d d 1 d 2 d 3 t t tlh, thl d(0:3), nd(0:3) sdata, nsdata clk , nclk (1) (1) rising edge causes serial data to be latched. clk4 , nclk4 (1) skip, nskip 1 t su t h + t c ------------------- - ? ? ? 360 phase margin = where t c is minimum clock cycle.
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 6 ? vitesse semiconductor corporation g52012-0 rev. 2.0 absolute maximum ratings (1) power supply voltage ( v ee ) ................................................................................................... v cc (gnd) to -6.0v ecl input voltage applied (2) ( v eclin ) ...........................................................................................-2.5v to + 0.5v high speed input voltage applied (2) ( v hsin ).....................................................................v ee -0.7v to v cc + 0.7v output current (output high) ( i out )..........................................................................................................-50 ma maximum junction temperature ( t j )............................................................................................................150 c case temperature under bias ( t c ) ................................................................................................ -55 o to + 125 o c storage temperature ( t stg ) ............................................................................................................ -65 o to + 150 o c notes: (1) caution: stresses listed under ?bsolute maximum ratings?may be applied to devices one at a time without causing permanent damage, but are stress ratings only. functionality at or exceeding the values listed is not implied. exposure to these values for extended periods may affect device reliability. (2) v ee must be applied before any input signal voltage (v eclin ). recommended operating conditions power supply voltage ( v ee ) .............................................................................................................-5.2v 0.26v operating temperature range* ( t )......................................(commercial) 0 o to 70 o c, (industrial) -40 o to + 85 o c * lower limit of speci?ation is ambient temperature and upper limit is case temperature.
? vitesse semiconductor corporation page 7 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse dc characteristics table 1: ecl inputs and outputs (over recommended operating conditions with internal v ref, v cc = gnd, output load = 50 ohms to -2.0v) note: 1) differential ecl output pairs must be terminated identically. 2) leakage currents exceed ecl speci?ations due to the internal bias network which is connected to all inputs table 2: power dissipation (over recommended operating conditions, v cc = gnd, outputs open circuit) table 3: high speed inputs (over recommended operating conditions, v cc = gnd, output load = 50 w to -2.0v) notes: 1) esd protection is not pr ovided for the high speed input pins, ther efore, proper procedur es should be used when handling this product. 2) a reference generator is built in to each high speed input, and these inputs are intended to be ac coupled. 3) if a high speed input is used single-ended, a 150 pf capacitor must be connected between the unused high speed or com- plement input and the power supply (v tt ). parameter description min typ max units conditions v oh output high voltage -1020 - -700 mv v in = v ih (max) or v il (min) v ol output low voltage -2000 - -1620 mv v in = v ih (max) or v il (min) v ih input high voltage -1040 - -600 mv guaranteed high signal for ecl inputs v il input low voltage -2000 - -1600 mv guaranteed low signal for ecl inputs i ih input high current - 500 1000 m a v in = v ih (max) i il input low current -1000 -500 - m a v in = v il (min) parameter description vs8004 (min) vs8004 (typ) vs8004 (max) vs8005 (min) vs8005 (typ) vs8005 (max) units i ee power supply current from v ee - 270 350 - 310 400 ma p d power dissipation 1.5 1.9 - 1.6 2.2 w parameter description min typ max units conditions v ih input high voltage -3.1 -3.0 -2.9 v guaranteed high signal v il input low voltage -4.1 -4.0 -3.9 v guaranteed low signal d v in input voltage swing 0.8 1.0 1.2 v ac coupled
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 8 ? vitesse semiconductor corporation g52012-0 rev. 2.0 table 4: high speed outputs (over recommended operating conditions, v cc = gnd, output load = 50 w to -2.0v) notes: 1) esd protection is not pr ovided for the high speed input pins, ther efore, proper procedur es should be used when handling parallel data, clk, nclk, skip, nskip inputs ecl inputs (clock or data) pro vide for a c coupled operation. internal biasing will position the reference voltage of approximately -1.32 volts on both the true and complement inputs. high speed inputs high speed inputs (clock or data) provide for a c coupled operation. internal biasing will position the refer - ence voltage of approximately -3.5 volts on both the true and complementary inputs. single-ended, ac coupled operation is illustrated below . parameter description min typ max units conditions v oh output high voltage - -0.9 - v terminated to -2.0v through 50 w v ol output low voltage - -1.8 - v terminated to -2.0v through 50 w d v out output voltage swing 0.8 1.0 1.4 v output load, 50 w to -2v 50 w chip boundary -1.32v 0.1 m f 0.1 m f -1.32v r ii = 1k w v cc = gnd v tt = -2v v tt v tt v tt = v cc -2v 50 w chip boundary -3.5v 150 pf 150 pf -3.5v r ii = 1k w v cc = gnd v ee = -5.2v v tt v tt
? vitesse semiconductor corporation page 9 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse figure 5: vs8004 pin diagram table 5: vs8004 pin description notes: 1) the heat sink is connected v ee (pin 25). to prevent a short circuit between v cc, v cca ( ? v normally) and v ee (-5.2v nor- mally), do not connect this heat sink to ground. ( ? v). pin # name i/o description 23, 24 clk, nclk i differential high speed clock inputs 27, 26 sdata, nsdata o differential high speed serial data outputs 17, 18 clk4, nclk4 o differential divide by 4 clock outputs (ecl) 7-10, 12-15 d( ?? :3), nd( ? :3) i differential parallel data inputs (ecl) 3, 5, 19, 25 (1) v ee -5.2v supply voltage 2, 4, 11, 20 v cc ? v ground connection 16, 28 v cca ? v output ground connection (normally connected to v cc ) 1, 6, 21, 22 nc no connection 25 26 22 23 24 27 28 14 13 12 11 10 9 8 1 2 3 4 5 6 7 21 20 19 18 17 16 15 nc nc vcc vee vcc vee d nc nd3 vcc vee nclk4 clk4 vcca nd2 nd d1 nd1 vcc d2 d3 vcca nc sdata nsdata vee nclk clk heat sink side vs8004
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 10 ? vitesse semiconductor corporation g52012-0 rev. 2.0 figure 6: vs8005 pin diagram table 6: vs8005 pin description notes: 1) the heat sink is connected to v ee (pin 25). to pr event a short cir cuit between v cc, v cca ( ? v normally) and v ee (-5.2v nor- mally), do not connect this heat sink to ground. 2) the falling edge of skip causes realignment of the parallel wor d boundary making parallel data invalid for thr ee clk4, nclk4 (12 clk, nclk) periods. pin # name i/o description 24, 23 clk, nclk i differential high speed clock inputs 26, 27 sdata, nsdata i differential high speed serial data outputs 17, 18 clk4, nclk4 o differential divide by 4 clock outputs (ecl) 7-10, 12-15 d( ?? :3), nd( ? :3) o differential parallel data outputs (ecl) 28, 1 skip, nskip i differential word boundary inputs (ecl) 3, 5, 19, 25 v ee -5.2v supply voltage 2, 4, 11, 20 v cc ? v ground connection 6, 16 v cca ? v output ground connection 21, 22 nc no connection nc nd3 vcc vee nclk4 clk4 vcca skip nc nsdata sdata vee clk nclk nd2 nd d1 nd1 vcc d2 d3 vcca nskip vcc vee vcc vee d vs8005 heat sink side 25 26 22 23 24 27 28 14 13 12 11 10 9 8 1 2 3 4 5 6 7 21 20 19 18 17 16 15
? vitesse semiconductor corporation page 11 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse package information item mm (min/max) in (min/max) item mm (min/max) in (min/max) a 11.176/11.682 0.440/0.460 k 0.102/0.203 0.004/0.008 b 1.016/1.524 0.040/0.060 l 5.842/6.858 0.230/0.270 c 8.128/8.636 0.33 typ m 22.860/25.398 0.900/1.000 e 1.143/1.397 0.050 typ n 0.356/0.559 0.014/0.022 i 0.406/0.610 0.016/0.024 o 1.525/2.287 0.075 typ j 1.829/2.235 .072/.088 m l k c i a j 45 n o heat sink side 28 1 e b b notes: drawing not to scale. package: ceramic (alumina); heat sink: copper-tungsten; leads: alloy 42 with gold plating. 28-pin leaded ceramic package (ldcc)
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 12 ? vitesse semiconductor corporation g52012-0 rev. 2.0 dut boards the vs8004fdut/vs8005fdut ev aluation boards are special purpose circuit boards which pro vide a test bed suitable for e v aluating the high performance characteristics of the vs8004 4:1 multiple x er or the vs8005 1:4 demultiplexer in the 28 pin leaded ceramic chip carrier. the gure belo w is a schematic representation of these circuit boards. these boards pro vide a controlled impedance transmission line for all signals, and suitable decoupling for the po wer supplies. the signal traces have a characteristic impedance of 50 w . all ecl input lines are terminated with 50 w (chip resistor) as close to the de vice package pin as possible. the high speed inputs are also pro vided with 150 pf blocking capacitors. signals are launched onto the circuit board and removed by means of sma coaxial connectors. while the input signals are terminated, the output signals are pro vided open circuit and are intended to be terminated in the mea- suring instrument. normally, the vs8004 and vs8005 operate in an ecl en vironment with standard ecl po wer buses: v and -5.2v . in order to simplify interf ace to standard ground referenced test equipment, ho wever , the circuit board po wer b uses are of fset so that the shield connectors are at ground v oltage. the gure belo w sho ws the arrangement of the po wer supply decoupling capacitors. there is a 33 m f electrolytic capacitor , as well as se v- eral 0.01 m f ceramic capacitors across each power bus. the de vice to be tested is held in place with a pressure retaining xture. the gure on the follo wing page indicates the physical dimensions and the connection labels for the evaluation boards. figure 7: vs8004/vs8005 dut board schematics high speed data or clock outputs: device under test v ee 50 w v cc 150 pf 0.01 m f 0.01 m f 0.01 m f 33 m f 33 m f + 2v - 3.2v ecl data or control inputs inp inp inp ecl data or clock outputs high speed clock inputs or high speed data inputs 50 w 50 w 0.01 m f 150 pf inp 50 w
? vitesse semiconductor corporation page 13 vs8004/8005 data sheet 2.5 gbits/sec 4-bit multiplex er/ demultiplexer chipset g52012-0 rev. 2.0 vitesse figure 8: vs8004/vs8005 dut boards notes: 1) this drawing represents both the vs8004fdut and vs8005fdut con gurations. (connection labels given in par enthe- ses are for the vs8005.) 2) nc = no connection. note: these connectors are omitted on the vs8004fdut version of this evaluation board. sdata (sdata) nsdata (nsdata) clk (clk) d2 (d2) nd2 (nd2) d3 (d3) gnd vcc vee 201-12x-x vs800x 7.0 " sq. clk4 (clk4) nclk (nclk) 0.75" (typ) barrier strip sma connector (typ) pin 1 nd3 (nd3) vite s s e semiconductor corporation device retaining clamp chip orientation indicator nd1 (nd1) d1 (d1) nd0 (nd0) d0 (d0) nclk4 (nclk4) nc (skip) nc (nskip)
vs8004/8005 vitesse data sheet 2.5 gbits/sec 4-bit multiplexer/ demultiplexer chipset page 14 ? vitesse semiconductor corporation g52012-0 rev. 2.0 ordering information v itesse products are a v ailable in a v ariety of packages and operating ranges. the order number for this product is formed by using a combination of the follo wing: device type, package type, and operating temper- ature range . notice v itesse semiconductor corporation reserv es the right to mak e changes in its products, speci cations or other information at an y time without prior notice. therefore the reader is cautioned to con rm that this datasheet is current prior to placing an y orders. the compan y assumes no responsibility for an y circuitry described other than circuitry entirely embodied in a vitesse product. warning vitesse semiconductor corporation s product are not intended for use in life support appliances, de vices or systems. use of a vitesse product in such applications without the written consent is prohibited. vs80xx f i temperature c: commercial (0 to 70 c) i: industrial (-40 to +85 c) package type f: leaded chip carrier (ldcc) device type vs8004: 2.5 gb/sec 4:1 multiplexer vs8005: 2.5 gb/sec 1:4 demultiplexer

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